In no particular order:

"List" doesn't work because DBGConsole resets the address in mPaneCP0Dis.SetAddress( g_dwPC );

Get rid of the old DPF() code (maybe make first param of DBGConsole_Msg() selectively print to logfile?)
Fix Lkb's new combiner to work with the new DX8 code
Check Lkb's savestate support still works with memory changes
Finish off dialog boxes for configuration

Implement skip/count
Check for pc crossing tlb boundary in dynarec

SR_Emit_Generic_R4300: Can move op to gCurrentOp in one instruction and restore inlining.

Should throw address error exceptions on mis-aligned loads/stores
Should be throwing Cop1 unusable exceptions if thread tries to access the FP regs...
Should be throwing reserved instruction exceptions for SPECIAL/REGIMM ops with undefined minor opcodes

Show countdown in debugger to next vbl/compare

Make sure count/compare works when skip > 1

Test for 1/2/8 byte write to hardware registers....need to see if real N64 ignores these


Create a batch/test mode that runs through all the roms and logs specific occurances..
	e.g. this could be used to check for any roms that require unimplemented stuff like reserved instruction exception.
	
Create a test mode to run dynarec/interpreting cores simultaneously and check for divergence. This could be automated too!

HW interrupts can't be cleared except through writting the HW regs (the two SW interrupts can be cleared)

Should SP_SET_INTR trigger an interrupt?

On FR, more 32 rather than 16 regs are available...check this

Try reading/writing to unused control registers - see if they always return 0 etc..

Does returning a random value for Rand cause problems??? It's meant to be random, but could be predictable...

Try re-enabling pending interrupts - check all count/compare, mi, etc

CAUSE should always match the enabled interrupts..assert this

Check PC for TLB misses etc...we could maybe reduce the number of tests by only recalculating the base PC address
when we transition over a 4k page (e.g. when we go from 0x????aFFC to 0x????b000).

Maybe g_dwPC could be added to g_pPCBase to form memory offset. Then only g_dwPC needs incrementing each cycle..

Could use exceptions to avoid testing gCPUStuffToDo each frame...need to see how this would work with dynarec.

Dynarec is missing exceptions/interrupts as it doesn't test gCPUStuffToDo each cycle

Check the value returned for the PRId register

BadVPN2 of context/xcontext register are not writable (and R in XContext)

Implement a test facility so it's possible to verify that "minor" changes aren't introducing bugs. 
We could have a CSynchroniser class which operates in either a "producer" or "consumer" mode. 
The producer shoves hashes of register/memory data to a data stream. This can be loaded back in in another
session by the consumer to ensure that the same sequence of data is seen. This data stream could be a file
(so testing an be carried out over a period of time) or a network connection/pipe to another instance of the emu.

Synch packets can be inserted using a macro. We could pass an optional argument into this (which can be eliminated
at compile time) to allow us to test with different levels of strictness.

Add a code to DbgConsole_Msg() which automatically pumps magenta text to the debug output (for unhandled scenarios etc).
This could be piped to a text file during automated test sessions etc.

Enable instrinsics

ResEvil writes to WatchLo/Hi

Observations from test rom
^^^^^^^^^^^^^^^^^^^^^^^^^^
Counter increases by different rate for different ops. nop is 0.5, mult 2.5 for example
VBL time in cycles appears to be V_SYNC_REG * 1500 - a small constant?
PIF DMA won't work if RDRAM transfer address isn't 8-byte aligned. Should investigate what happens...
The CRC values calculated for reads/writes to page 0x400 seem to be negated..need to test this with rumble pack inserted.


When an interrupt is unmasked with a write to MI_INTR_MASK_REG, any pending interrupts will fire.
Any interrupts pending following an ERET WILL cause them to fire again (if unmasked). e.g. the interrupt will keep firing until dealt with properly


/* A test running the pif rom with different values for the cic
cic: 0x00000000
r0:*00000000 *t0:000000f0 s0:00000000  t8:00000000
at: 00000000 *t1:00000000 s1:00000000  t9:d73f2993
v0: d1731be9 *t2:00000040 s2:00000000 *k0:00000000
v1: d1731be9 *t3:a4000000 s3:00000000 *k1:00000000
a0: 00001be9 t4: d1330bc3 s4:00000001 *gp:00000000
a1: f45231e5 t5: d1330bc3 s5:00000000 *sp:a4001ff0
a2:*a4001f0c t6: 25613a26 s6:00000000 *s8:00000000
a3:*a4001f08 t7: 2ea04317 s7:00000000 *ra:a4001550
  
0xcdcdcdcd
r0:*00000000 *t0:000000f0 s0:00000000  t8:00000002
at: 00000001 *t1:00000000 s1:00000000  t9:688076ac
v0: 57ab3f3c *t2:00000040 s2:00000000 *k0:00000000
v1: 57ab3f3c *t3:a4000000 s3:00000001 *k1:00000000
a0: 00003f3c  t4:1c9fac27 s4:00000001 *gp:00000000
a1: 05825895  t5:112fe29d s5:00000000 *sp:a4001ff0
a2:*a4001f0c  t6:191df4b2 s6:000000cd *s8:00000000
a3:*a4001f08  t7:eafcd1fc s7:00000001 *ra:a4001550

0xffffffff
r0:*00000000 *t0:000000f0 s0:00000000  t8:00000000
at: 00000000 *t1:00000000 s1:00000000  t9:a4e54e8c
v0: 4a882c3f *t2:00000040 s2:00000000 *k0:00000000
v1: 4a882c3f *t3:a4000000 s3:00000001 *k1:00000000
a0: 00002c3f  t4:4ceb6550 s4:00000001 *gp:00000000
a1: 6848e133  t5:4ceb6550 s5:00000001 *sp:a4001ff0
a2:*a4001f0c  t6:24a38463 s6:000000ff *s8:00000000
a3:*a4001f08  t7:3257a25f s7:00000001 *ra:a4001550

*/



Done:
^^^^^

For ease of maintenance, make WriteMappedValue use WriteMapped (or a common function...)
Move breakpoint index to OpCode field.
